Pipeline Burst Cache
PB Cache
Pipelined Burst Cache

    (PB Cache) A synchronous cache built
   from pipelined SRAM.

   A cache in which reading or writing a new location takes
   multiple cycles but subsequent locations can be accessed in
   a single cycle.  On Pentium systems in 1996, pipeline burst
   caches are frequently used as secondary caches.  The first 8
   bytes of data are transferred in 3 CPU cycles, and the
   next 3 8-byte pieces of data are transferred in one cycle
   each.

   (1996-10-13)