Advanced RISC Machine

    (ARM, Originally Acorn RISC Machine).  A series
   of low-cost, power-efficient 32-bit RISC microprocessors
   for embedded control, computing, digital signal processing,
   games, consumer multimedia and portable applications.  It
   was the first commercial RISC microprocessor (or was the MIPS
   R2000?) and was licensed for production by Asahi Kasei
   Microsystems, Cirrus Logic, GEC Plessey Semiconductors,
   Samsung, Sharp, Texas Instruments and VLSI Technology.

   The ARM has a small and highly orthogonal instruction set,
   as do most RISC processors.  Every instruction includes a
   four-bit code which specifies a condition (of the processor
   status register) which must be satisfied for the instruction
   to be executed.  Unconditional execution is specified with a
   condition "true".

   Instructions are split into load and store which access memory
   and arithmetic and logic instructions which work on
   registers (two source and one destination).

   The ARM has 27 registers of which 16 are accessible in any
   particular processor mode.  R15 combines the program counter
   and processor status byte, the other registers are general
   purpose except that R14 holds the return address after a
   subroutine call and R13 is conventionally used as a stack
   pointer.  There are four processor modes: user, interrupt
   (with a private copy of R13 and R14), fast interrupt (private
   copies of R8 to R14) and supervisor (private copies of R13
   and R14).  The ALU includes a 32-bit barrel-shifter
   allowing, e.g., a single-cycle shift and add.

   The first ARM processor, the ARM1 was a prototype which was
   never released.  The ARM2 was originally called the Acorn RISC
   Machine.  It was designed by Acorn Computers Ltd. and used
   in the original Archimedes, their successor to the BBC
   Micro and BBC Master series which were based on the
   eight-bit 6502 microprocessor.  It was clocked at 8 MHz
   giving an average performance of 4 - 4.7 MIPS.  Development
   of the ARM family was then continued by a new company,
   Advanced RISC Machines Ltd.

   The ARM3 added a fully-associative on-chip cache and
   some support for multiprocessing.  This was followed by the
   ARM600 chip which was an ARM6 processor core with a
   4-kilobyte 64-way set-associative cache, an MMU based on
   the MEMC2 chip, a write buffer (8 words?) and a
   coprocessor interface.

   The ARM7 processor core uses half the power of the ARM6
   and takes around half the die size.  In a full processor
   design (ARM700 chip) it should provide 50% to 100% more
   performance.

   In July 1994 VLSI Technology, Inc. released the ARM710
   processor chip.

   Thumb is an implementation with reduced code size
   requirements, intended for embedded applications.

   An ARM800 chip is also planned.

   AT&T, IBM, Panasonic, Apple Coputer, Matsushita and
   Sanyo either rely on, or manufacture, ARM 32-bit processor
   chips.

   Usenet newsgroup: <news:comp.sys.arm>.

   (1997-08-05)