AMD 29000
A RISC microprocessor descended from the
Berkley RISC design. Like the SPARC design that was
introduced shortly afterward, the 29000 has a large register
set split into local and global sets. But though it was
introduced before the SPARC, it has a more elegant method of
register management.
The 29000 has 64 global registers, in comparison to the
SPARC's eight. In addition, the 29000 allows variable sized
windows allocated from the 128 register stack cache. The
current window or stack frame is indicated by a stack pointer,
a pointer to the caller's frame is stored in the current
frame, like in an ordinary stack (directly supporting stack
languages like C, a CISC-like philosophy). Spills and
fills occur only at the ends of the cache, and registers are
saved/loaded from the memory stack. This allows variable
window sizes, from 1 to 128 registers. This flexibility, plus
the large set of global registers, makes register allocation
easier than in SPARC.
There is no special condition code register - any general
register is used instead, allowing several condition codes to
be retained, though this sometimes makes code more complex.
An instruction prefetch buffer (using burst mode) ensures
a steady instruction stream. To reduce delays caused by a
branch to another stream, the first four new instructions are
cached and next time a cached branch (up to sixteen) is taken,
the cache supplies instructions during the initial memory
access delay.
Registers aren't saved during interrupts, allowing the
interrupt routine to determine whether the overhead is
worthwhile. In addition, a form of register access control is
provided. All registers can be protected, in blocks of 4,
from access. These features make the 29000 useful for
embedded applications, which is where most of these processors
are used, allowing it the claim to be "the most popular RISC
processor". The 29000 also includes an MMU and support for
the AMD 29027 FPU.
(1995-06-19)
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